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843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 1 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator g eneral d escription the ics843021 is a gigabit ethernet clock generator and a member of the hiperclocks tm family of high performance devices from ics. the ics843021 uses a 25mhz crystal to synthesize 125mhz. the ics843021 has excellent phase jitter performance, over the 1.875mhz ? 20mhz integration range. the ics843021 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? 1 differential 3.3v lvpecl output ? crystal oscillator interface designed for 22.4mhz - 28mhz, 18pf parallel resonant crystal ? output frequency range: 112mhz - 140mhz ? vco range: 560mhz to 700mhz ? output duty cycle range: 49% - 51% ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.37ps (typical) ? rms phase noise at 125mhz (typical) offset noise p o w er 100hz ............... -94.2 dbc/hz 1khz .............. -122.8 dbc/hz 10khz .............. -132.2 dbc/hz 100khz .............. -131.3 dbc/hz ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request ? lead-free package fully rohs compliant hiperclocks? ics ics843021 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v cca v ee xtal_out xtal_in 1 2 3 4 v cc q0 nq0 nc 8 7 6 5 b lock d iagram p in a ssignment osc phase detector vco 5 25 (fixed) xtal_in xtal_out nq0 q0 25mhz f requency t able - t ypical a pplications s t u p n i ) z h m ( y c n e u q e r f t u p t u o ) z h m ( y c n e u q e r f l a t s y r c 5 25 2 1 6 . 6 23 3 1
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 2 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a c c r e w o p. n i p y l p p u s g o l a n a 2v e e r e w o p. n i p y l p p u s e v i t a g e n 4 , 3 , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 5c nd e s u n u. t c e n n o c o n 7 , 60 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e r o c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 3 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator t able 3a. p ower s upply dc c haracteristics , v cc = 3.3v10%, t a =0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 7 9 . 23 . 33 6 . 3v v a c c e g a t l o v y l p p u s g o l a n a 7 9 . 23 . 33 6 . 3v i e e t n e r r u c y l p p u s r e w o p 5 8a m t able 3b. lvpecl dc c haracteristics , v cc = 3.3v10%, t a =0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 - t able 5. ac c haracteristics , v cc = 3.3v10%, t a =0c to 70c t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f 1 e t o n ; y c n e u q e r f 4 10 4z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p . e g n a r o c v o t e u d z h m 8 2 - z h m 4 . 2 2 f o e g n a r a o t d e t i m i l s i y c n e u q e r f t u p n i : 1 e t o n a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 101.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 1 10 4 1z h m t ) ? ( t i j , r e t t i j e s a h p s m r 1 e t o n ; ) m o d n a r ( z h m 5 2 1 ) z h m 0 2 o t z h m 5 7 8 . 1 : e g n a r n o i t a r g r e t n i ( 7 3 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 5 5s p c d oe l c y c y t u d t u p t u o 9 41 5% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 4 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator t ypical p hase n oise at 125mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.37ps (typical) phase noise result by adding a 10 gb ethernet filter to raw data raw phase noise data 10 gb ethernet filter ? ? ? o ffset f requency (h z ) dbc hz n oise p ower
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 5 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.33v clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = q0 nq0 v ee v cc rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 6 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator a pplication i nformation figure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics843021 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843021 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , and v cca should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 7 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator a pplication s chematic figure 3a shows a schematic example of the ics843021. an example of lvepcl termination is shown in this schematic. additional lvpecl termination approaches are shown in the lvpecl termination application note. in this example, an 18pf parallel resonant 25mhz crystal is used for generating 125mhz output frequency. the c1 = 27pf and c2 = 33pf are recom- mended for frequency accuracy. for different board layout, the c1 and c2 values may be slightly adjusted for optimizing fre- quency accuracy. f igure 3a. ics843021 s chematic e xample f igure 3b. ics843021 pc b oard l ayout e xample pc b oard l ayout e xample figure 3b shows an example of ics843021 p.c. board layout. the crystal x1 footprint shown in this example allows installa- tion of either surface mount hc49s or through-hole hc49 pack- age. the footprints of other components in this example are listed in the table 6. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. t able 6. f ootprint t able e c n e r e f e re z i s 2 c , 1 c2 0 4 0 3 c5 0 8 0 5 c , 4 c3 0 6 0 2 r3 0 6 0 t n e n o p m o c s t s i l , 6 e l b a t : e t o n . e l p m a x e t u o y a l s i h t n i n w o h s s e z i s zo = 50 ohm vcc x1 25mhz vcc=3.3v c3 10uf vcc c1 27pf q c5 0.1u r3 133 c2 33pf vcc zo = 50 ohm u1 ics843011 1 2 3 4 8 7 6 5 vcca vee xtal _o u t xtal _i n vcc q0 nq0 nc r4 82.5 c4 0.01u r5 133 nq vcca r6 82.5 18pf r2 10 + - ics843021
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 8 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843021. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843021 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.63v * 85ma = 308.6mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.63v, with all outputs switching) = 308.6mw + 30mw = 338.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.339w * 90.5c/w = 100.7c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 8- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w note: most modern pcb designs use multi-layered boards.
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 9 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 3. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 3. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 10 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ics843021 is: 1928 t able 7. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 11 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator p ackage o utline - g s uffix for 8 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 12 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 1 2 0 3 4 8 s c ia 1 2 0 3p o s s t d a e l 8e b u tc 0 7 o t c 0 t g a 1 2 0 3 4 8 s c ia 1 2 0 3p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l g a 1 2 0 3 4 8 s c il a 1 2 0p o s s t " e e r f - d a e l " d a e l 8e b u tc 0 7 o t c 0 t f l g a 1 2 0 3 4 8 s c il a 1 2 0p o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademarks, hiperclocks? and femtoclocks? are a trademark of integrated circuit systems, inc. or its subsi diaries in the united states and/or other countries.
843021ag www.icst.com/products/hiperclocks.html rev. c march 31, 2005 13 integrated circuit systems, inc. ics843021 f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 4 t 5 t 1 3 3 . e l b a t n o i t c n u f d e d d a . s t e l l u b e g n a r o c v & y c n e u q e r f t u p t u o , l a t s y r c d e t a d p u - n o i t c e s s e r u t a e f o t l a c i p y t z h m 5 2 m o r f y c n e u q e r f d e g n a h c - e l b a t s c i t s i r e t c a r a h c l a t s y r c . 1 e t o n d e d d a . x a m z h m 0 4 d n a . n i m z h m 4 1 o t l a c i p y t z h m 5 2 1 m o r f y c n e u q e r f t u p t u o d e g n a h c - e l b a t s c i t s i r e t c a r a h c c a . x a m z h m 0 4 1 d n a . n i m z h m 2 1 1 4 0 / 6 / 0 1 b9 t2 1 0 0 1 o t e b u t r e p 4 5 1 m o r f t n u o c d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 5 1 / 0 1 c a 3 t3 v d e s a e r c n i - e l b a t y l p p u s r e w o p c c d e t c e l f e r s i d n a % 5 m o r f % 0 1 v 3 . 3 o t . t e e h s a t a d e h t t u o h g u o r h t 4 0 / 3 / 1 1 c 6 t 7 t 9 t 3 8 0 1 2 1 . w o l f r i a e c n a d e p m i l a m r e h t e g a k c a p d e t c e r r o c - s g n i t a r m u m i x a m e t u l o s b a . w o l f r i a d e t c e r r o c - e l b a t e c n a t s i s e r l a m r e h t . e l b a t n i w o l f r i a d e t c e r r o c . g n i k r a m d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 0 3 / 1 1 c 9 t 1 2 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 1 3 / 3

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